Soft errors involve changes to data, rather than changes to a physical circuit. A soft error, unlike many other errors, may be recoverable, for example, by rewriting the data. Soft errors may occur on transmission lines, in digital logic, in analog circuits, semiconductor storage elements and elsewhere. Oftentimes, soft errors are caused by neutrons from cosmic rays and alpha particles emitted from integrated circuit packaging material (soft error sources), although other causes are also possible.
Soft errors may be caused by package radioactive decay that results in the emission of an alpha particle. Soft errors may also be caused by neutrons. A neutron may undergo neutron capture by a nucleus of an atom, producing an unstable isotope that in turn may cause a soft error when the isotope decays producing an alpha particle.
A soft error may occur when an alpha particle hits a transistor device, transferring a charge to a sensitive node of the device that alters a data value stored in the device. A soft error may result in improper operation. For example, a soft error may alter the program code stored in the memory of a microprocessor resulting in improper microprocessor operation. Such an error may be referred to as a soft error because the affected program code may be rewritten to restore proper microprocessor operation.
A circuit may be prone to soft errors when its critical charge value, the minimum electron charge disturbance needed to flip its logic state, becomes too low. A circuit's critical charge value may be a function of capacitance and voltage. A circuit with a higher critical charge value may result in less sensitivity to soft errors, but also may result in a slower device having higher power dissipation. As device geometries continue to shrink and supply voltages continue to decrease for performance reasons, devices may become more prone to soft errors.
Soft errors may be a serious issue for memory cells because their critical charges may be very small. Error correcting codes may be implemented in memory modules to reduce soft errors. As integrated circuit processes continue to shrink feature sizes, the critical charge for logic circuits, such as static combinational logic and sequential elements, may become small enough to be less than the charges generated by alpha particles. In microprocessors, network processors and network storage controllers, the overall soft error rate for a state of the art design may be on the order of 40% for unprotected SRAM, 11% for combinational logic and 49% for sequential elements. Because the soft error rate of sequential elements, such as latches and flip-flops, may exceed that of unprotected SRAMs, sequential elements with reduced soft error rates may be needed.
FIG. 1 depicts a storage element 10 employing a conventional configuration of back-to-back inverters 12, 14 as a storage node in a sequential element such as a latch or flip-flop, also sometimes referred to as a “keeper.” The inverters 12, 14 may maintain the voltage level on a storage node 16. FIG. 2 depicts a conventional CMOS implementation of the storage element 10 of FIG. 1. Each inverter 12, 14 may include a PMOS transistor 18, 20, respectively, and an NMOS transistor 22, 24, respectively. Node 26 may initially be in a logic one state with the NMOS transistor 22 on and the PMOS transistor 18 off. An alpha particle hitting the node 26 around the active region of NMOS transistor 24 may drain the charge stored on the node 26 to a supply node Vss, causing the node 26 to flip to the opposite logic state, a logic zero. This causes the NMOS transistor 22 to turn off and PMOS transistor 18 to turn on, flipping the logic state of the following output node from a logic zero to a logic one. Thus, the stored data in the storage element 10 is altered by the alpha particle hit. This change of logic state is a soft error.
The node 26 may also be in a logic zero state with the PMOS transistor 18 on and the NMOS transistor 22 off. An alpha particle hitting the node 26 around the active region of PMOS transistor 20 can source the charge from a supply node vdd to the node 26 and cause the node to flip from a logic zero to a logic one. This causes the NMOS transistor 22 to turn on and the PMOS transistor 18 to turn off, flipping the logic state of the following output node from a logic one to a logic zero. Thus, the stored data in the storage element 10 is altered by the alpha particle hit.
FIG. 3 depicts a latch 30 employing a keeper-type storage element 32, which may be implemented by back-to-back inverters, for example. When a clock CLK is at a logic one, a transmission gate 34 of the latch 30 may become transparent. While the transmission gate 34 is transparent, the upstream combinational logic may drive the D input of the latch 30 and may write the corresponding logic value into the storage element 32. During this time, any soft error that affects the transistors inside the latch 30 may have a negligible effect because the correct logic value is being driven at the D input of the latch. However, when the clock input of the latch 30 is at a logic zero, i.e., when the latch is holding a logic state, a soft error may flip the latch state. Thus, the latch 30 may be more susceptible to soft errors when the storage element 32 of the latch is holding a logic state.
As technology trends continue toward increasingly smaller feature sizes, system level soft errors may become more frequent and may become an issue, for example, for enterprise servers and networking hardware. Current soft error protection techniques may include circuit-level hardening, classical hardware redundancy, and time redundancy techniques. However, such techniques may introduce additional latency. Certain high performance circuits may not be able to tolerate the additional latency introduced by these soft error protection techniques.
What is needed is a storage node that recovers from soft errors without adversely affecting latency. Such a storage node may be employed in sequential storage elements such as latches and flip-flops and memory cells to minimize the effects of soft errors on circuit operation and/or stored memory state.